dsPIC Microcrocontrollers Introduction ( adapted from microchip )

Let us start by looking at the basic concept behind the dsPIC30F Digital Signal Controller architecture.

Now, what exactly is a Digital Signal Controller, or DSC? A DSC is a single-chip embedded controller that integrates the control attributes of a microcontroller, or MCU, with the computational efficiency and throughput of a Digital Signal Processor, or DSP. The dsPIC30F is Microchip’s first family designed specifically to address the DSC market space.

The dsPIC30F family encompasses a wide range of performance requirements, making it an ideal architecture for anyone considering a 16-bit MCU or DSP, or even a 32-bit MCU. The devices were designed to provide a familiar look and feel to MCU users, especially users familiar with PIC® MCUs. The DSP features were seamlessly integrated to ease adoption by new users of DSP technology. Moreover, the pricing structure of dsPIC30F devices make them affordable for embedded control applications.

The dsPIC30F devices were architected from the grounds-up to provide all the features a user would expect from an industry leading 16-bit MCU. A rich instruction set, coupled with extensive addressing modes, operate on a generous set of general purpose working registers and a software stack. The result is very good C compiler efficiency. All the devices use Flash memory technology for its Program Memory and Data EEPROM, in order to provide maximum manufacturing cycle time flexibility. Fast, in-circuit self programming technology enables remote updating of Program Memoryand Data EEPROM. The high reliability of the Flash memory enables 40 years of data retention and up to one million program or erase cycles at 85 degrees Centigrade. Competitive DSP performance is enabled by a powerful set of DSP features. A single-cycle 17-by-17 Multiplier; two 40-bit accumulators and a 40-bit barrel shifter; zero overhead Do and Repeat loops; rounding or saturation of results; and special addressing mode support for circular buffers and FFT’s. The dsPIC30F architecture also supports a very flexible interrupt processing structure. Each device includes an extensive set of peripheral modules, inc luding timers, serial subsystems, and analog to digital converter channels. Some devices also contain advanced peripherals geared towards specific applications like motor control, audio, or internet connectivity. Last but by no means the least, the devices contain hardware logic that enables in-circuit debugging and Flash programming without removing the device from the board.

 
Key Features

• High performance 16-bit CPU designed for optimum C compiler efficiency

• Flexible, reliable FLASH program memory

• Competitive DSP performance

• Fast, deterministic interrupt system

• Advanced peripheral I/O features

• Fast, precise 10 & 12-bit A to D Converters

• Data EEPROM and SRAM

• In-Circuit debug capabilities

The dsPIC30F devices can operate at instruction execution speeds up to 30 MIPS. All the devices use Flash memory, and can operate in the Extended temperature range up to 125 degrees Centigrade. They are available in two speed categories: a 20 MIPS version and a 30 MIPS version. A wide range of device packaging options are supported for each device, from the tiny 28-pin QFN packages to the larger Dual Inline packages and large-pin-count Quad Flat Pack packages.

This table shows a comparison of the estimated average throughput of a dsPIC30F with respect to other 16-bit MCU and DSP competitors. An instruction frequency analysis was performed on the compiled results of an industry standard Automotive benchmark suite. The results were then applied to the other instruction set architectures. This instruction profile was used as the basis for calculating the average throughput for these devices.

As you can see, the dsPIC30F has the highest average throughput among its peer group, even compared to devices that operate at higher instruction cycle rates. This is to a large extent a result of the powerful data addressing capabilities, and due to the fact that unlike other architectures a vast majority of the dsPIC30F instructions execute in a single cycle. This ability to attain higher average throughputs at relatively lower instruction cycle rates also provides power consumption benefits.

The dsPIC30F architecture was designed for optimum compiler efficiency. As demonstrated by these charts, INEX C30 C Compiler for dsPIC30F devices generates more compact 16-bit application code than other 16-bit MCUs. The dsPIC30F handles even 32-bit application code very efficiently, which is particularly noteworthy if one is considering the dsPIC30F architecture for 32-bit applications.

The dsPIC30F architecture provides a high-performance yet low-cost solution that addresses the majority of embedded signal processing applications. To prove the point, here is some benchmark data from BDTI, an independent DSP industry benchmarking firm. This table compares the instruction cycle count for each device to execute a certain set of DSP algorithms or ‘building blocks’, with the dsPIC30F results normalized to a value of ‘1’. As you can see, the performance of the dsPIC30F compares favorably with other embedded control DSP devices. This emphasizes the efficacy and versatility of the dsPIC30F CPU architecture. The dsPIC30F performs especially well in executing the Control benchmark, which is essentially a state machine application. This demonstrates the efficiency of the dsPIC30F in performing typical embedded control tasks, without compromising on the DSP aspects of its functionality.